/* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * CMSPAR, some architectures can't have space and mark parity. */ #ifndef CMSPAR #define CMSPAR 0 #endif /* * Major and minor numbers. */ #define XR_USB_SERIAL_TTY_MAJOR 266 #define XR_USB_SERIAL_TTY_MINORS 32 /* * Requests. */ #define USB_RT_XR_USB_SERIAL (USB_TYPE_CLASS | USB_RECIP_INTERFACE) /* * Output control lines. */ #define XR_USB_SERIAL_CTRL_DTR 0x01 #define XR_USB_SERIAL_CTRL_RTS 0x02 /* * Input control lines and line errors. */ #define XR_USB_SERIAL_CTRL_DCD 0x01 #define XR_USB_SERIAL_CTRL_DSR 0x02 #define XR_USB_SERIAL_CTRL_BRK 0x04 #define XR_USB_SERIAL_CTRL_RI 0x08 #define XR_USB_SERIAL_CTRL_FRAMING 0x10 #define XR_USB_SERIAL_CTRL_PARITY 0x20 #define XR_USB_SERIAL_CTRL_OVERRUN 0x40 /* * Internal driver structures. */ /* * The only reason to have several buffers is to accommodate assumptions * in line disciplines. They ask for empty space amount, receive our URB size, * and proceed to issue several 1-character writes, assuming they will fit. * The very first write takes a complete URB. Fortunately, this only happens * when processing onlcr, so we only need 2 buffers. These values must be * powers of 2. */ #define XR_USB_SERIAL_NW 16 #define XR_USB_SERIAL_NR 16 #define RAMCTL_BUFFER_PARITY 0x1 #define RAMCTL_BUFFER_BREAK 0x2 #define RAMCTL_BUFFER_FRAME 0x4 #define RAMCTL_BUFFER_OVERRUN 0x8 /* Soft flag stuffed by wide_rx tee — not from chip RAMCTL. */ #define POG422_RAMCTL_HS 0x10 /* POG422 fork 1I: DTtty RX ring size (must precede struct xr_usb_serial). */ #define POG422_DTTTY_RX_SIZE 8192u /* EG 2.2.1.15: wide RX tee (pairs); buffer is 2 × pairs bytes interleaved. */ #ifndef POG422_WIDE_RX_SIZE #define POG422_WIDE_RX_SIZE 8192u #endif struct xr_usb_serial_wb { unsigned char *buf; dma_addr_t dmah; int len; int use; struct urb *urb; struct xr_usb_serial *instance; }; struct xr_usb_serial_rb { int size; unsigned char *base; dma_addr_t dma; int index; struct xr_usb_serial *instance; }; struct reg_addr_map { unsigned int uart_enable_addr; unsigned int uart_format_addr; unsigned int uart_flow_addr; unsigned int uart_loopback_addr; unsigned int uart_xon_char_addr; unsigned int uart_xoff_char_addr; unsigned int uart_gpio_mode_addr; unsigned int uart_gpio_dir_addr; unsigned int uart_gpio_set_addr; unsigned int uart_gpio_clr_addr; unsigned int uart_gpio_status_addr; unsigned int uart_gpio_int_mask_addr; unsigned int uart_customized_int_addr; unsigned int tx_break_addr; unsigned int uart_custom_driver; unsigned int uart_low_latency; }; struct xr_usb_serial { struct usb_device *dev; /* the corresponding usb device */ struct usb_interface *control; /* control interface */ struct usb_interface *data; /* data interface */ struct tty_port port; /* our tty port data */ struct urb *ctrlurb; /* urbs */ u8 *ctrl_buffer; /* buffers of urbs */ dma_addr_t ctrl_dma; /* dma handles of buffers */ u8 *country_codes; /* country codes from device */ unsigned int country_code_size; /* size of this buffer */ unsigned int country_rel_date; /* release date of version */ struct xr_usb_serial_wb wb[XR_USB_SERIAL_NW]; unsigned long read_urbs_free; struct urb *read_urbs[XR_USB_SERIAL_NR]; struct xr_usb_serial_rb read_buffers[XR_USB_SERIAL_NR]; int rx_buflimit; int rx_endpoint; spinlock_t read_lock; int write_used; /* number of non-empty write buffers */ int transmitting; spinlock_t write_lock; struct mutex mutex; bool disconnected; struct usb_cdc_line_coding line; /* bits, stop, parity */ struct work_struct work; /* work queue entry for line discipline waking up */ /* EG 2.2.2.10: async MANUAL_DE hard-cap — drop GPIO7 if userspace stalls. */ struct delayed_work de_cap_work; atomic_t de_manual_held; unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */ unsigned int ctrlout; /* output control lines (DTR, RTS) */ unsigned int writesize; /* max packet size for the output bulk endpoint */ unsigned int readsize,ctrlsize; /* buffer sizes for freeing */ unsigned int minor; /* xr_usb_serial minor number */ unsigned char clocal; /* termios CLOCAL */ unsigned int ctrl_caps; /* control capabilities from the class specific header */ unsigned int susp_count; /* number of suspended interfaces */ unsigned int combined_interfaces:1; /* control and data collapsed */ unsigned int is_int_ep:1; /* interrupt endpoints contrary to spec used */ unsigned int throttled:1; /* actually throttled */ unsigned int throttle_req:1; /* throttle requested */ u8 bInterval; struct xr_usb_serial_wb *delayed_wb; /* write queued for a device about to be woken */ unsigned int channel; int preciseflags; /* USB: wide mode, TTY: flags per character */ int trans9; /* USB: wide mode, serial 9N1 */ int have_extra_byte; int extra_byte; atomic64_t rx_chars_inserted; /* RX bytes delivered (DTtty ring or tty flip) */ atomic64_t rx_urbs_completed; /* RX URBs with actual_length > 0 */ /* POG422 fork 1I: DTtty RX ring — uartd reads via ioctl, not read()/FIONREAD */ bool dttty_rx; u8 dttty_buf[POG422_DTTTY_RX_SIZE]; unsigned int dttty_head; unsigned int dttty_tail; u64 dttty_total_written; u32 dttty_overruns; /* EG 2.2.1.15: wide RX tee — [data][flags] pairs; independent of dttty */ bool wide_rx; u8 wide_rx_buf[POG422_WIDE_RX_SIZE * 2]; unsigned int wide_rx_head; /* pair index */ unsigned int wide_rx_tail; u64 wide_rx_total_written; /* pairs */ u32 wide_rx_overruns; unsigned short DeviceVendor; unsigned short DeviceProduct; struct reg_addr_map reg_map; bool rs485_422_en; /* POG422: XR21B142x Table-8 customized GPIO interrupt (SLV-IN on GPIO1/CD) */ bool customized_int_enabled; u16 last_gpio_state; u16 last_gpio_int; u8 last_slv_in_active; u64 last_gpio1_event_ns; u32 gpio1_event_count; wait_queue_head_t gpio1_wait; spinlock_t gpio1_lock; /* EG 2.2.1: GPIO5 RS485_EN_ACT fall → USB interrupt IN → TX empty wake */ u8 last_gpio5_tx_active; u32 tx_empty_event_count; wait_queue_head_t tx_empty_wait; /* * EG 3.0.1.6: runtime-gated timing ring (always compiled; off by default). * Independent of POG422_HW_DEBUG (that path changes uartd RX drain). */ #ifndef POG422_TIMING_RING_MAX #define POG422_TIMING_RING_MAX 256u #endif u8 timing_enabled; u32 timing_head; u32 timing_count; u32 timing_dropped; u64 timing_total_pushed; u64 timing_ts[POG422_TIMING_RING_MAX]; u32 timing_type[POG422_TIMING_RING_MAX]; u16 timing_gpio_state[POG422_TIMING_RING_MAX]; u16 timing_gpio_int[POG422_TIMING_RING_MAX]; u8 timing_flags[POG422_TIMING_RING_MAX]; u16 timing_nbytes[POG422_TIMING_RING_MAX]; u64 timing_rx_chars[POG422_TIMING_RING_MAX]; #if defined(POG422_HW_DEBUG) && (POG422_HW_DEBUG) #ifndef POG422_HWDBG_EDGE_MAX #define POG422_HWDBG_EDGE_MAX 256u #endif /* Table-8 USB INT edge ring (GPIO1 + GPIO5) — compile-out for prod */ u64 hwdbg_ts[POG422_HWDBG_EDGE_MAX]; u16 hwdbg_gpio_state[POG422_HWDBG_EDGE_MAX]; u16 hwdbg_gpio_int[POG422_HWDBG_EDGE_MAX]; u8 hwdbg_flags[POG422_HWDBG_EDGE_MAX]; u32 hwdbg_head; u32 hwdbg_count; u32 hwdbg_dropped; #endif }; #define CDC_DATA_INTERFACE_TYPE 0x0a /* constants describing various quirks and errors */ #define NO_UNION_NORMAL 1 #define SINGLE_RX_URB 2 #define NO_CAP_LINE 4 #define NOT_A_MODEM 8 #define NO_DATA_INTERFACE 16 #define IGNORE_DEVICE 32 #define UART_ENABLE_TX 1 #define UART_ENABLE_RX 2 #define UART_GPIO_CLR_DTR 0x8 #define UART_GPIO_SET_DTR 0x8 #define UART_GPIO_CLR_RTS 0x20 #define UART_GPIO_SET_RTS 0x20 #define LOOPBACK_ENABLE_TX_RX 1 #define LOOPBACK_ENABLE_RTS_CTS 2 #define LOOPBACK_ENABLE_DTR_DSR 4 #define UART_FLOW_MODE_NONE 0x0 /* bit3 must stay 0 — Half-Duplex mutes RX */ #define UART_FLOW_MODE_HW 0x1 #define UART_FLOW_MODE_SW 0x2 #define UART_GPIO_MODE_SEL_GPIO 0x0 #define UART_GPIO_MODE_SEL_RTS_CTS 0x1 /* POG422 SLV-OUT (GPIO7): RS485 auto half-duplex (datasheet CDC default 0x0339). */ #define POG422_GPIO_MODE_RS485_AUTO 0x0339 /* * EG 2.2.1: GPIO7 = manual DE (bits[6:5]=00, bit4=0). * GPIO5/RTS = RS485_EN_ACT active-high (bits[2:0]=011, bit3=1) — sense-only TX * activity for USB interrupt IN (Table-8). Does NOT drive bus DE. * High byte 0x03 keeps TXT/RXT enable like 0x0300/0x0339. */ #define POG422_GPIO_MODE_MANUAL_SLV 0x030B #define POG422_GPIO7_BIT 0x80 #define POG422_GPIO5_BIT 0x20 #define POG422_GPIO_STD_DIR 0x28 /* DTR + RTS as outputs */ #define POG422_GPIO7_DIR (POG422_GPIO_STD_DIR | POG422_GPIO7_BIT) /* INT mask: 0=edge IRQ enabled. Unmask GPIO1 (HS) + GPIO5 (TX-done sense). */ #define POG422_GPIO_INT_MASK_TXDONE 0x03D0 /* Assert (1) / release (0) SLV-OUT on the open tty (1N manual GPIO7 mode). */ int pog422_set_gpio7_sl_out(struct xr_usb_serial *xr_usb_serial, int tx_enable); #define XR2280x_FUNC_MGR_OFFSET 0x40 int xr_usb_serial_pre_setup(struct xr_usb_serial *xr_usb_serial); int xr_usb_serial_set_wide_mode(struct xr_usb_serial *xr_usb_serial, int preciseflags); int pog422_set_b142x_wide_tx_only(struct xr_usb_serial *xr_usb_serial, int enable); int pog422_b142x_wait_tx_wire_idle(struct xr_usb_serial *xr_usb_serial, u32 frame_len, unsigned int timeout_ms, unsigned int margin_us); void xr_usb_serial_pog422_rs485_probe_finish(struct xr_usb_serial *xr_usb_serial); void xr_usb_serial_set_flow_mode(struct xr_usb_serial *xr_usb_serial, struct tty_struct *tty, unsigned int cflag);