POG422 Pi handshake / FPC mapping

Design notes for moving M-S and OIS handshake lines off XR UART GPIO onto Seeed Dual Ethernet J19 (3.3 V level-shifted). Export of agent response, 2026-08-10.

Mapping kit for when the flex lands — grounded in what’s already true in the tree, with the 5.52 M-S / OIS names and the Seeed Dual GbE J19 FPC as the Pi landing.

1. Rename (docs / silk / schematics)

Software still says SLV_* / GPIO7 heavily; rename can trail the PCB. Prefer new names on the flex silk + netlist first.

2. What those four nets are today (XR path)

On the XR21B1422 hat (present software path), effective roles are:

Important bus rule (unchanged with new names): only the sender drives HS; peers wait for idle. Drop HS mid-frame and T340+ trashes the packet. Spec: FIXTURE_TOPOLOGY.md SLV-HS section + XR README channel/GPIO table.

Physics on Rev D HAT: RS-422 sense is often 5 V-domain (SLV_HS at LED/R6); TXS0108E makes 3.3 V SLV-IN into the XR. Your new path is: post TXS / 3.3 V clean logic → flex → Seeed J19 → CM GPIO. Keep all four nets 3.3 V class at the FPC; never put 5 V on RP1/CM I/O.

3. Seeed landing: J19 I/O FPC (limited)

Documented in HS_GPIO_TAP.md (Seeed CM4 Dual GbE, J19 Molex 525590834). Verified physical map 2026-08-11 (j19_io_mapper + probe). Seeed schematic sheet 13 is reversed vs FPC pad order — use this table only:

So the flex should be labeled with both:

1. Connector pin number (1–8)
2. Intended electrical net (M-S_IN, LED1, …)

And bring-up must map pin→BCM by electrical test, not by PDF alone.

Six data pins used (four HS + two LEDs). Fan pins GPIO12/17 stay committed.

4. Recommended net → strip / J19 assignment (verified 2026-08-11)

Strip pin = 0.5 mm FPC breakout pin 1…8 (same numbers as j19_io_mapper physical walk). HS on SPI bank; status LEDs on GPIO2/3 (disable dtparam=i2c_arm).

4a. Status LEDs (LED1 / LED2)

Two green indicators only — not the HAT DS1 bargraph (DS1 is hardwired to bus signals). ~2–5 mA; no external driver.

• LED feed = HAT VDD (local); only cathode/sink crosses FPC to the Pi.
• GPIO high or release = LED off.
• EG and DF each own one LED — no dual writers.
• Uses: heartbeat, boot POST, operational OK blink (helpers to land later).

# Suggested software constants
EG_STATUS_LED_GPIO=2    # strip pin 5, LED1 EtherGold
DF_STATUS_LED_GPIO=3    # strip pin 6, LED2 DyzineFrame
# Active-low: write 0 = on, 1 = off

Do not put HS _OUT nets on strip pins 5–6 (GPIO2/3) — reserved for LED1/LED2.

Active level for M-S: today active-high on manual GPIO7 assert for TX DE; HS sense polarity on the tap was active-low LED domain — your 3.3 V post-TXS nets may be inverted relative to LED (same as current XR SI). Capture polarity once on the flex nets with a scope/logger before software assumes.

4b. HAT J5 vs Seeed strip (netlist v2, 2026-08-11)

Source: POG-COM-PI-HAT-REV_E__Netlist_v3.txt. FPC is signal-only (no rails). Jumpers select who drives OUT: center pin = *_OUT_3.3, outer pins = UART vs PI.

Status LEDs are on the HAT, fed from HAT VDD (regulator) through R11/R12 (470 Ω), not from Seeed DCDC_3V3 over the flex. Current return: HAT VDD → R → LED → J5 → Pi GPIO sink → Pi/USB ground bond → HAT GND.

5. Mapping process (when flex arrives)

Treat this as a signed pin map artifact, not a one-time guess.

1. Cold continuity
   Flex unplugged: ohm-test HAT pad → FFC pad → expected pin number.
2. Dead-Pi pinctrl sweep (all 6 signals)
   With flex plugged, no POG bus traffic:

   # For each candidate BCM on J19: enable internal pull up, then down, watch line.
   pinctrl get 2 3 8 9 10 11
   # For OUT nets: briefly drive high/low under controlled script;
   # confirm HAT side at TXS A-side / OUT pad.

   Fill:

   Net	J19 pin	Measured BCM	Dir	Idle level	Active on TX / peer HS

3. Single-net live proof
   • Only M-S_OUT: manually assert/release around a known inject; confirm HS LED/scope.
   • Only M-S_IN: peer TX; edge count vs copper.
   • Repeat OIS.
4. Lock file
   e.g. /etc/ethergold/hs_gpio.env / pog422_hs_pi.env:

   MS_OUT_GPIO=11
   MS_IN_GPIO=9
   OIS_OUT_GPIO=10
   OIS_IN_GPIO=8
   MS_ACTIVE_HIGH=1
   OIS_ACTIVE_HIGH=1

   Same pattern as today’s HS_GPIO_LINE=3 for the diagnostic tap.
5. Software phase (later, separate rev)
   Today DE/sense is XR ioctl (SET_GPIO7, GET_SLV_IN, table-8 GPIO INT). Pi-native path means uartd/inject grow a gpiod / sysfs backend while UART stays on XRUSB — that is the big software revisiting, not the flex day-one. Mapping first.

6. What to freeze on the flex this week

• Net names: M-S_IN, M-S_OUT, OIS_IN, OIS_OUT, GND, optional 3V3
• Series 0 Ω / TVS / series-R options near Pi for bring-up
• Clear FPC pin 1 orientation mark (easy to reverse a flex and lose a day)
• Prefer not relying on schematic GPIO numbers alone for pin 1–8; put pad nets in silkscreen order as signal names
• Leave two free pins for EN_ACT sense or a second M-S sense if you later split RX/drive domains

7. Open decisions (for you / next session)

1. Active levels of the four 3.3 V nets (post-shift): match XR today or invert once at the flex and say so in silk?
2. OIS_OUT: stay hardware-auto (tied to OIS UART TX sense) vs always software-driven like M-S? Software prefers software-driven for clean DE.
3. Will M-S_IN/OUT still be galvanically the same RS-422 pair, or separate single-ended already after the HAT front-end? (matters for which pad you label OUT vs IN)
4. After flex BOM is fixed, write POG422_PI_HS_MAP.md (or extend HS_GPIO_TAP.md) with the measured table and config keys — before coding the Pi GPIO backend.